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74LVQ161 Datasheet

  • 74LVQ161

  • SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

  • 13頁(yè)

  • ETC

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74LVQ161
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 180 MHz (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
=25擄C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
75鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 161
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVQ161M
T&R
74LVQ161MTR
74LVQ161TTR
DESCRIPTION
The 74LVQ161 is a low voltage CMOS
SYNCHRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology. It is
ideal for low power and low noise 3.3V
applications. It is a 4 bit binary counter with
Asynchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
PIN CONNECTION AND IEC LOGIC SYMBOLS
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (PE) and Count Enable Carry Input
(TE), determine the mode of operation as shown
in the Truth Table. A LOW signal on CLEAR
overrides counting and parallel loading and sets
all outputs on LOW state. A LOW signal on LOAD
overrides counting and allows information on
Parallel Data Qn inputs to be loaded into the
flip-flops on the next rising edge of CLOCK. With
LOAD and CLEAR, PE and TE permit counting
when both are high. Conversely, a LOW signal on
either PE and TE inhibits counting. All inputs and
outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
July 2001
1/13

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