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74LVQ08 Datasheet

  • 74LVQ08

  • QUAD 2-INPUT AND GATE

  • 11頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74LVQ08
LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 5.6 ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 2碌A(chǔ)(MAX.) at T
A
=25擄C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
75鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 08
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ08MTR
74LVQ08TTR
DESCRIPTION
The 74LVQ08 is a low voltage CMOS QUAD
2-INPUT AND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 2 stages
including buffer output, which enables high noise
immunity and stable output.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 5
1/11

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