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74LVCHR32245AZKER Datasheet

  • 74LVCHR32245AZKER

  • 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

  • 249.56KB

  • 11頁

  • TI

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SN74LVCHR32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES601 鈥?AUGUST 2004 鈥?REVISED SEPTEMBER 2005
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Member of the Texas Instruments Widebus+鈩?/div>
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t
pd
of 4.8 ns at 3.3 V
Input and Output Ports Have Equivalent 26-鈩?/div>
Series Resistors, So No External Resistors
Are Required
Typical V
OLP
(Output Ground Bounce) <0.8 V
at V
CC
= 3.3 V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot) >2 V at
V
CC
= 3.3 V, T
A
= 25擄C
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
鈥?/div>
鈥?/div>
I
off
Supports Partial-Power-Down Mode
Operation
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V
V
CC
)
Other Products to Consider: SN74LVC32245,
SN74LVCH32245A, SN74LVCR32245A
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
DESCRIPTION/ORDERING INFORMATION
This 32-bit (quad-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V V
CC
operation.
The SN74LVCHR32245A is designed for asynchronous communication
control-function implementation minimizes external timing requirements.
between
data
buses.
The
This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows
data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses
are effectively isolated.
The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of this device for down
translation in a mixed-voltage environment.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-鈩?resistors to reduce overshoot and
undershoot.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input
circuit and is not disabled by OE or DIR.
ORDERING INFORMATION
T
A
鈥?0擄C to 85擄C
(1)
LFBGA 鈥?GKE
LFBGA 鈥?ZKE (Pb-free)
PACKAGE
(1)
Tape and reel
ORDERABLE PART NUMBER
SN74LVCHR32245AKR
74LVCHR32245AZKER
TOP-SIDE MARKING
LQ245A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2004鈥?005, Texas Instruments Incorporated

74LVCHR32245AZKER 產(chǎn)品屬性

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器

  • 74LVCHR

  • 收發(fā)器，非反相

  • 4

  • 8

  • 12mA，12mA

  • 1.65 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 96-LFBGA

  • 96-PBGA MICROSTAR（13.6x5.6）

  • 帶卷 (TR)

  • 296-18354-2

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