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74LVCE161284VRG4 Datasheet

  • 74LVCE161284VRG4

  • 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE...

  • 16頁

  • TI

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www.ti.com
SN74LVCE161284
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
SCES541 鈥?JANUARY 2004 鈥?REVISED MARCH 2005
FEATURES
鈥?/div>
Auto-Power-Up Feature Prevents Printer
Errors When Printer Is Turned On, But No
Valid Signal Is at A9鈥揂13 Pins
1.4-k鈩?Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors
Designed for IEEE Std 1284-I (Level-1 Type)
and IEEE Std 1284-II (Level-2 Type) Electrical
Specifications
Flow-Through Architecture Optimizes PCB
Layout
I
off
and Power-Up 3-State Support Hot
Insertion
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection
鈥?/div>
鹵4
kV 鈥?Human-Body Model
鈥?/div>
鹵8
kV 鈥?IEC 61000-4-2, Contact Discharge
(Connector Pins)
鈥?/div>
鹵15
kV 鈥?IEC 61000-4-2, Air-Gap Discharge
(Connector Pins)
鈥?/div>
鹵15
kV 鈥?Human-Body Model
(Connector Pins)
DGG OR DL PACKAGE
(TOP VIEW)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
HD
A9
A10
A11
A12
A13
V
CC
A1
A2
GND
A3
A4
A5
A6
GND
A7
A8
V
CC
PERI LOGIC IN
A14
A15
A16
A17
HOST LOGIC OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DIR
Y9
Y10
Y11
Y12
Y13
V
CC
CABLE
B1
B2
GND
B3
B4
B5
B6
GND
B7
B8
V
CC
CABLE
PERI LOGIC OUT
C14
C15
C16
C17
HOST LOGIC IN
DESCRIPTION/ORDERING INFORMATION
The SN74LVCE161284 is designed for 3-V to 3.6-V V
CC
operation. This device provides asynchronous two-way
communication between data buses. The control-function implementation minimizes external timing
requirements.
This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR)
is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and
four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive
the PERI LOGIC line.
ORDERING INFORMATION
T
A
0擄C to 70擄C
SSOP 鈥?DL
TSSOP 鈥?DGG
(1)
PACKAGE
(1)
Tube
Tape and reel
Tape and reel
ORDERABLE PART NUMBER
SN74LVCE161284DL
SN74LVCE161284DLR
SN74LVCE161284DGGR
TOP-SIDE MARKING
LVCE161284
LVCE161284
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2004鈥?005, Texas Instruments Incorporated

74LVCE161284VRG4 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 邏輯 - 專用邏輯

  • 74LVC

  • IEEE STD 1284 轉(zhuǎn)換收發(fā)器

  • 3 V ~ 3.6 V

  • 19

  • 0°C ~ 70°C

  • 表面貼裝

  • 48-TFSOP（0.173"，4.40mm 寬）

  • 48-TVSOP

  • 帶卷 (TR)

74LVCE161284VRG4相關(guān)型號PDF文件下載

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