SCES210K 鈭?APRIL 1999 鈭?REVISED OCTOBER 2003
SN74LVC2G241
DUAL BUFFER/DRIVER
WITH 3 STATE OUTPUTS
D
Available in the Texas Instruments
D
D
D
D
D
D
D
D
D
D
NanoStar錚?and NanoFree錚?Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 4.1 ns at 3.3 V
Low Power Consumption, 10-碌A(chǔ) Max I
CC
鹵24-mA
Output Drive at 3.3 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25擄C
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
鈭?2000-V Human-Body Model (A114-A)
鈭?200-V Machine Model (A115-A)
鈭?1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE
(TOP VIEW)
1OE
1A
2Y
GND
1
2
3
4
8
7
6
5
V
CC
2OE
1Y
2A
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
GND
2Y
1A
1OE
4 5
3 6
2 7
1 8
2A
1Y
2OE
V
CC
description/ordering information
This dual buffer/line driver is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC2G241 is designed specifically to improve both the performance and density of 3-state
memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
ORDERING INFORMATION
TA
PACKAGE鈥?/div>
NanoStar錚?鈭?WCSP (DSBGA)
0.17-mm Small Bump 鈭?YEA
NanoFree錚?鈭?WCSP (DSBGA)
0.17-mm Small Bump 鈭?YZA (Pb-free)
NanoStar錚?鈭?WCSP (DSBGA)
0.23-mm Large Bump 鈭?YEP
NanoFree錚?鈭?WCSP (DSBGA)
0.23-mm Large Bump 鈭?YZP (Pb-free)
SSOP 鈭?DCT
VSSOP 鈭?DCU
Reel of 3000
Reel of 3000
Reel of 250
Reel of 3000
SN74LVC2G241YEPR
SN74LVC2G241YZPR
SN74LVC2G241DCTR
SN74LVC2G241DCUR
SN74LVC2G241DCUT
C41_
C41_ _ _
ORDERABLE
PART NUMBER
SN74LVC2G241YEAR
SN74LVC2G241YZAR
_ _ _C2_
TOP-SIDE
MARKING鈥?/div>
鈭?0擄C to 85擄C
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
鈥?DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb,
鈥?/div>
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1
74LVC2G241DCUTE4 產(chǎn)品屬性
74LVC2G241DCUTE4相關(guān)型號(hào)PDF文件下載
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QUADRUPLE 2 INPUT POSITIVE NAND GATES
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Quad 2-input NAND gate
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Quad 2-input NAND gate
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Quad 2-input NAND gate
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Quad 2-input NAND gate
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