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74LVC2G132DCURE4 Datasheet

  • 74LVC2G132DCURE4

  • DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

  • 238.34KB

  • 13頁

  • TI

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SN74LVC2G132
DUAL 2-INPUT NAND GATE
WITH SCHMITT-TRIGGER INPUTS
www.ti.com
SCES547A 鈥?FEBRUARY 2004 鈥?REVISED JUNE 2005
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Available in Texas Instruments NanoStar鈩?/div>
and NanoFree鈩?Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 5.3 ns at 3.3 V
Low Power Consumption, 10-碌A(chǔ) Max I
CC
鹵24-mA
Output Drive at 3.3 V
Typical V
OLP
(Output Ground Bounce) <0.8 V
at V
CC
= 3.3 V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot) >2 V at
V
CC
= 3.3 V, T
A
= 25擄C
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE
(TOP VIEW)
1A
1B
2Y
GND
1
2
3
4
8
7
6
5
V
CC
1Y
2B
2A
YEP OR YZP PACKAGE
(BOTTOM VIEW)
GND
2Y
1B
1A
4 5
3 6
2 7
1 8
2A
2B
1Y
V
CC
DESCRIPTION/ORDERING INFORMATION
This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A
鈰?/div>
B or Y = A + B in positive
logic. The device functions as two independent inverters, but because of Schmitt action, it has different input
threshold levels for positive-going (V
T+
) and negative-going (V
T-
) signals.
NanoStar鈩?and NanoFree鈩?package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar鈩?鈥?WCSP (DSBGA)
0.23-mm Large Bump 鈥?YEP
NanoFree鈩?鈥?WCSP (DSBGA)
0.23-mm Large Bump 鈥?YZP
(Pb-free)
SSOP 鈥?DCT
VSSOP 鈥?DCU
(1)
(2)
Reel of 3000
SN74LVC2G132YZPR
Reel of 3000
Reel of 3000
Reel of 250
SN74LVC2G132DCTR
SN74LVC2G132DCUR
SN74LVC2G132DCUT
C3B_ _ _
C3B_
ORDERABLE PART NUMBER
SN74LVC2G132YEPR
_ _ _D5_
TOP-SIDE MARKING
(2)
鈥?0擄C to 85擄C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
鈰?/div>
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2004鈥?005, Texas Instruments Incorporated

74LVC2G132DCURE4 產(chǎn)品屬性

  • 3,000

  • 集成電路 (IC)

  • 邏輯 - 柵極和逆變器

  • 74LVC

  • 與非門

  • 2

  • 2

  • 施密特觸發(fā)器

  • 1.65 V ~ 5.5 V

  • 10µA

  • 32mA，32mA

  • 0.39 V ~ 1.87 V

  • 1.16 V ~ 3.33 V

  • 5ns @ 5V，50pF

  • -40°C ~ 85°C

  • 表面貼裝

  • US8

  • 8-VFSOP（0.091"，2.30mm 寬）

  • 帶卷 (TR)

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