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74LVC2G125DCTRE6 Datasheet

  • 74LVC2G125DCTRE6

  • DUAL BUS BUFFER GATE WITH 3 STATE OUTPUTS

  • 13頁

  • TI

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SN74LVC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES204K 鈥?APRIL 1999 鈥?REVISED JUNE 2005
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Available in the Texas Instruments
NanoStar鈩?and NanoFree鈩?Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 4.3 ns at 3.3 V
Low Power Consumption, 10-碌A(chǔ) Max I
CC
鹵24-mA
Output Drive at 3.3 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25擄C
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE
(TOP VIEW)
1OE
1A
2Y
GND
1
2
3
4
8
7
6
5
V
CC
2OE
1Y
2A
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
GND
2Y
1A
1OE
4 5
3 6
2 7
1 8
2A
1Y
2OE
V
CC
DESCRIPTION/ORDERING INFORMATION
The SN74LVC2G125 is a dual bus buffer gate, designed for 1.65-V to 5.5-V V
CC
operation. This device features
dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is
high.
NanoStar鈩?and NanoFree鈩?package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar鈩?鈥?WCSP (DSBGA)
0.17-mm Small Bump 鈥?YEA
NanoFree鈩?鈥?WCSP (DSBGA)
0.17-mm Small Bump 鈥?YZA (Pb-free)
鈥?0擄C to 85擄C
NanoStar鈩?鈥?WCSP (DSBGA)
0.23-mm Large Bump 鈥?YEP
NanoFree鈩?鈥?WCSP (DSBGA)
0.23-mm Large Bump 鈥?YZP (Pb-free)
SSOP 鈥?DCT
VSSOP 鈥?DCU
(1)
(2)
Reel of 3000
Reel of 3000
Reel of 250
ORDERABLE PART NUMBER
SN74LVC2G125YEAR
SN74LVC2G125YZAR
Reel of 3000
SN74LVC2G125YEPR
SN74LVC2G125YZPR
SN74LVC2G125DCTR
SN74LVC2G125DCUR
SN74LVC2G125DCUT
C25_ _ _
C25_
_ _ _CM_
TOP-SIDE MARKING
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
鈥?/div>
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 1999鈥?005, Texas Instruments Incorporated

74LVC2G125DCTRE6 產(chǎn)品屬性

  • 1

  • 集成電路 (IC)

  • 邏輯 - 緩沖器,驅(qū)動(dòng)器,接收器,收發(fā)器

  • 74LVC

  • 緩沖器/線路驅(qū)動(dòng)器,非反相

  • 2

  • 1

  • 32mA,32mA

  • 1.65 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 7-LSSOP(0.11"?,2.80mm 寬)

  • SM8

  • Digi-Reel®

  • 296-32006-6

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