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74LVC1G386DCKRG4 Datasheet

  • 74LVC1G386DCKRG4

  • SINGLE 3-INPUT POSITIVE-XOR GATE

  • 268.33KB

  • 12頁

  • TI

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SN74LVC1G386
SINGLE 3-INPUT POSITIVE-XOR GATE
SCES439C 鈥?APRIL 2003 鈥?REVISED APRIL 2005
FEATURES
鈥?/div>
Available in the Texas Instruments
NanoStar 鈩?and NanoFree鈩?/div>
Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
DBV OR DCK PACKAGE
(TOP VIEW)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
A
GND
B
1
2
3
6
5
4
C
V
CC
Y
YEP OR YZP PACKAGE
(BOTTOM VIEW)
B
GND
A
3 4
2 5
1 6
Y
V
CC
C
DESCRIPTION/ORDERING INFORMATION
The SN74LVC1G386 performs the Boolean function Y = A
鈯?/div>
B
鈯?/div>
C in positive logic.
NanoStar鈩?and NanoFree鈩?package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar鈩?鈥?WCSP (DSBGA)
0.23-mm Large Bump 鈥?YEP
鈥?0擄C to 85擄C
NanoFree鈩?鈥?WCSP (DSBGA)
0.23-mm Large Bump 鈥?YZP (Pb-free)
SOT (SOT-23) 鈥?DBV
SOT (SC-70) 鈥?DCK
(1)
(2)
ORDERABLE PART NUMBER
SN74LVC1G386YEPR
Tape and reel
SN74LVC1G386YZPR
Tape and reel
Tape and reel
SN74LVC1G386DBVR
SN74LVC1G386DCKR
CC6_
C8_
_ _ _C8_
TOP-SIDE MARKING
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
鈰?/div>
= Pb-free).
FUNCTION TABLE
INPUTS
A
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
C
L
H
L
H
L
H
L
H
OUTPUT
Y
L
H
H
L
H
L
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2003鈥?005, Texas Instruments Incorporated

74LVC1G386DCKRG4 產(chǎn)品屬性

  • 3,000

  • 集成電路 (IC)

  • 邏輯 - 柵極和逆變器

  • 74LVC

  • XOR（異或）

  • 1

  • 3

  • -

  • 1.65 V ~ 5.5 V

  • 10µA

  • 32mA，32mA

  • 0.7 V ~ 0.8 V

  • 1.7 V ~ 2 V

  • 4ns @ 5V，50pF

  • -40°C ~ 85°C

  • 表面貼裝

  • SC-70-6

  • 6-TSSOP，SC-88，SOT-363

  • 帶卷 (TR)

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