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74LVC1G175GW Datasheet

  • 74LVC1G175GW

  • Single D-type flip-flop with reset; positive-edge trigger

  • 17頁(yè)

  • PHILIPS

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74LVC1G175
Single D-type 鏗俰p-鏗俹p with reset; positive-edge trigger
Rev. 01 鈥?18 October 2004
Product data sheet
1. General description
The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior
to most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully speci鏗乪d for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging back鏗俹w current through the device when
it is powered down.
The 74LVC1G175 is a single positive edge triggered D-type 鏗俰p-鏗俹p with individual
data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operate independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
2. Features
s
s
s
s
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V).
鹵24
mA output drive (V
CC
= 3.0 V)
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Speci鏗乪d from
鈭?0 擄C
to +85
擄C
and
鈭?0 擄C
to +125
擄C.
s
s
s
s
s
s
s
s

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