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74LS93 Datasheet

  • 74LS93

  • Decade and Binary Counters

  • 10頁(yè)

  • NSC

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DM74LS90 DM74LS93 Decade and Binary Counters
June 1989
DM74LS90 DM74LS93
Decade and Binary Counters
General Description
Each of these monolithic counters contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the 鈥橪S90 and divide-
by-eight for the 鈥橪S93
All of these counters have a gated zero reset and the LS90
also has gated set-to-nine inputs for use in BCD nine鈥檚 com-
plement applications
To use their maximum count length (decade or four bit bina-
ry) the B input is connected to the Q
A
output The input
count pulses are applied to input A and the outputs are as
described in the appropriate truth table A symmetrical di-
vide-by-ten count can be obtained from the 鈥橪S90 counters
by connecting the Q
D
output to the A input and applying the
input count to the B input which gives a divide-by-ten square
wave at output Q
A
Features
Y
Y
Typical power dissipation 45 mW
Count frequency 42 MHz
Connection Diagrams
(Dual-In-Line Packages)
TL F 6381 鈥?1
Order Number DM74LS90M or DM74LS90N
See NS Package Number M14A or N14A
TL F 6381 鈥?2
Order Number DM74LS93M or DM74LS93N
See NS Package Number M14A or N14A
C
1995 National Semiconductor Corporation
TL F 6381
RRD-B30M105 Printed in U S A

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