DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
SN54/74LS90
SN54/74LS92
SN54/74LS93
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
鈥?/div>
Low Power Consumption . . . Typically 45 mW
鈥?/div>
High Count Rates . . . Typically 42 MHz
鈥?/div>
Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary
鈥?/div>
Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
LOADING
(Note a)
HIGH
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Clock (Active LOW going edge) Input to
梅2
Section
Clock (Active LOW going edge) Input to
梅5
Section (LS90),
梅6
Section (LS92)
Clock (Active LOW going edge) Input to
梅8
Section (LS93)
Master Reset (Clear) Inputs
Master Set (Preset-9, LS90) Inputs
Output from
梅2
Section (Notes b & c)
Outputs from
梅5
(LS90),
梅6
(LS92),
梅8
(LS93) Sections (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
LOW
1.5 U.L.
14
14
1
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
1
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
碌A(chǔ)
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b.
Temperature Ranges.
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
LOGIC SYMBOL
LS90
6 7
1 2
MS
CP0
CP1
MR Q0 Q1 Q2 Q3
1 2
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PINS 4, 13
14
1
CP0
CP1
MR Q0 Q1 Q2 Q3
1 2
6 7 12 11 9 8
VCC = PIN 5
GND = PIN 10
NC = PINS 2, 3, 4, 13
14
1
CP0
CP1
MR Q0 Q1 Q2 Q3
1 2
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PIN 4, 6, 7, 13
LS92
LS93
14
1
FAST AND LS TTL DATA
5-90
MOTOROLA
1
2
3
4
5
6
