OCTAL BUS TRANSCEIVERS
These octal bus transceivers are designed for asynchronous two-way
communication between data buses. Control function implementation
minimizes external timing requirements. These circuits allow data transmis-
sion from the A bus to B or from the B bus to A bus depending upon the logic
level of the direction control (DIR) input. Enable input (G) can disable the
device so that the buses are effectively isolated.
DEVICE
LS640
LS641
LS642
LS645
OUTPUT
3-State
Open-Collector
Open-Collector
3-State
LOGIC
Inverting
True
Inverting
True
SN54/74LS640
SN54/74LS641
SN54/74LS642
SN54/74LS645
OCTAL BUS TRANSCEIVERS
LOW POWER SCHOTTKY
FUNCTION TABLE
CONTROL
INPUTS
G
L
L
H
DIR
L
H
X
LS640
LS642
B data to A bus
A data to B bus
Isolation
OPERATION
LS641
LS645
B data to A bus
A data to B bus
Isolation
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
H = HIGH Level, L = LOW Level, X = Irrelevant
20
1
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
CONNECTION DIAGRAMS DIP
(TOP VIEW)
ENABLE
VCC G
B1
20 19 18
B2
17
B3
16
B4
15
B5
14
B6
13
B7
12
B8
11
ENABLE
VCC G
B1
20 19 18
B2
17
B3
16
B4
15
B5
14
B6
13
B7
12
B8
11
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND
SN54 / 74LS640
SN54 / 74LS642
SN54 / 74LS641
SN54 / 74LS645
FAST AND LS TTL DATA
5-1
1
2
3
