SN54/74LS48
BCD TO 7-SEGMENT
DECODER
The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND
gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates
and one driver are connected in pairs to make BCD data and its complement
available to the seven decoding AND-OR-INVERT gates. The remaining
NAND gate and three input buffers provide lamp test, blanking input/ripple-
blanking input for the LS48.
The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on
the state of the auxiliary inputs, decodes this data to drive other components.
The relative positive logic output levels, as well as conditions required at the
auxiliary inputs, are shown in the truth tables.
The LS48 circuit incorporates automatic leading and / or trailing edge
zero-blanking control (RBI and RBO). Lamp Test (LT) may be activated any
time when the BI / RBO node is HIGH. Both devices contain an overriding
blanking input (BI) which can be used to control the lamp intensity by varying
the frequency and duty cycle of the BI input signal or to inhibit the outputs.
鈥?/div>
Lamp Intensity Modulation Capability (BI/RBO)
鈥?/div>
Internal Pull-Ups Eliminate Need for External Resistors
鈥?/div>
Input Clamp Diodes Eliminate High-Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
f
15
g
14
a
13
b
12
c
11
d
10
e
9
D SUFFIX
SOIC
CASE 751B-03
BCD TO 7-SEGMENT
DECODER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
1
B
2
C
3
4
5
6
D
7
A
8
GND
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
a
LT BI / RBO RBI
LOGIC DIAGRAM
Ceramic
Plastic
SOIC
A
b
B
INPUT
C
D
d
BLANKING INPUT OR
RIPPLE-BLANKING
OUTPUT
c
OUTPUT
LOGIC SYMBOL
7 1 2 6 3 5
A B C D LT RBI
SN54 / 74LS48
a
b c d
e
BI/
f g RBO
e
13 12 11 10 9 15 14 4
VCC = PIN 16
GND = PIN 8
RIPPLE-BLANKING
INPUT
LAMP-TEST
INPUT
f
g
FAST AND LS TTL DATA
5-59
1
2
3
