DM74LS298 Quad 2-Port Register Multiplexer with Storage
October 1988
Revised March 2000
DM74LS298
Quad 2-Port Register Multiplexer with Storage
General Description
The DM74LS298 is a quad 2-port register. It is the logical
equivalent of a quad 2-input multiplexer followed by a quad
4-bit edge-triggered register. A Common Select input
selects between two 4-bit input ports (data sources). The
selected data is transferred to the output register synchro-
nous with the HIGH-to-LOW transition of the Clock input.
Features
s
Select from two data sources
s
Fully edge-triggered operation
s
Typical power dissipation of 65 mW
Ordering Code:
Order Number
DM74LS298N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
V
CC
=
Pin 16
GND
=
Pin 8
Pin Descriptions
Pin Names
S
CP
I0
a
, I0
d
I1
a
, I1
d
Q
a
, Q
d
Description
Common Select Inputs
Clock Pulse Input (Active Falling Edge)
Source 0 Data Inputs
Source 1 Data Inputs
Flip-Flip Outputs
Truth Table
Inputs
S
l
l
h
h
I0
x
l
h
X
X
I1
x
X
X
l
h
Output
Q
x
L
H
L
H
l
=
LOW Voltage Level one setup time prior to the HIGH-to-LOW clock
transition.
h
=
HIGH Voltage Level one setup time prior to the HIGH-to-LOW clock
transition.
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
漏 2000 Fairchild Semiconductor Corporation
DS009826
www.fairchildsemi.com
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