鈥?/div>
8-Bit High Speed Register
Parallel Register
Common Clock and Master Reset
Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
20
Q7
19
D7
18
D6
17
Q6
16
Q5
15
D5
14
D4
13
Q4
12
CP
11
OCTAL D FLIP-FLOP
WITH CLEAR
LOW POWER SCHOTTKY
20
1
J SUFFIX
CERAMIC
CASE 732-03
1
MR
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
10
GND
20
1
N SUFFIX
PLASTIC
CASE 738-03
PIN NAMES
LOADING
(Note a)
HIGH
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
CP
D0 鈥?D7
MR
Q0 鈥?Q7
Clock (Active HIGH Going Edge) Input
Data Inputs
Master Reset (Active LOW) Input
Register Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
20
1
DW SUFFIX
SOIC
CASE 751D-03
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
碌A
HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
TRUTH TABLE
MR
L
H
H
CP
X
Dx
X
H
L
Qx
L
H
L
H = HIGH Logic Level
L = LOW Logic Level
X = Immaterial
LOGIC DIAGRAM
11
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
CP
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
1
MR
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
FAST AND LS TTL DATA
5-447
1
2
3
4
5
