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74LS197 Datasheet

  • 74LS197

  • 4-STAGE PRESETTABLE RIPPLE COUNTERS

  • 8頁(yè)

  • MOTOROLA   MOTOROLA

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4-STAGE PRESETTABLE
RIPPLE COUNTERS
The SN54/74LS196 decade counter is partitioned into divide-by-two and di-
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)
sequence or in a bi-quinary mode producing a 50% duty cycle output. The
SN54/74LS197 contains divide-by-two and divide-by-eight sections which
can be combined to form a modulo-16 binary counter. Low Power Schottky
technology is used to achieve typical count rates of 70 MHz and power dis-
sipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)
overrides clocked operations and asynchronously loads the data on the Par-
allel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits
usable as programmable counters. The circuits can also be used as 4-bit
latches, loading data from the Parallel Data inputs when PL is LOW and stor-
ing the data when PL is HIGH.
SN54/74LS196
SN54/74LS197
4-STAGE PRESETTABLE
RIPPLE COUNTERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
14
1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Low Power Consumption 鈥?Typically 80 mW
High Counting Rates 鈥?Typically 70 MHz
Choice of Counting Modes 鈥?BCD, Bi-Quinary, Binary
Asynchronous Presettable
Asynchronous Master Reset
Easy Multistage Cascading
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
14
MR
13
Q3
12
P3
11
P1
10
Q1
9
CP0
8
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
1
PL
2
Q2
3
P2
4
P0
5
Q0
6
CP1
7
GND
PIN NAMES
LOADING
(Note a)
HIGH
LOW
1.5 U.L.
1.75 U.L.
0.8 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
8
6
LOGIC SYMBOL
1
PL
4 10 3 11
P0 P1 P2 P3
CP0
CP1 (LS196)
CP1 (LS197)
MR
PL
P0鈥揚(yáng)3
Q0鈥換3
Clock (Active LOW Going Edge)
Input to Divide-by-Two Section
Clock (Active LOW Going Edge)
Input to Divide-by-Five Section
Clock (Active LOW Going Edge)
Input to Divide-by-Eight Section
Master Reset (Active LOW) Input
Parallel Load (Active LOW) Input
Data Inputs
Outputs (Notes b, c)
1.0 U.L.
2.0 U.L.
1.0 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
CP0
CP1
MR
13
Q0 Q1 Q2 Q3
5
9 2 12
VCC = PIN 14
GND = PIN 7
NOTES:
a. 1 TTL Unit Load (U.L.) = 40碌A(chǔ) HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
c. In addition to loading shown, Q0 can also drive CP1.
FAST AND LS TTL DATA
5-372

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