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74LS192 Datasheet

  • 74LS192

  • PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BIN...

  • 278.34KB

  • 9頁

  • MOTOROLA   MOTOROLA

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PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the
SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate
Count Up and Count Down Clocks are used and in either counting mode the
circuits operate synchronously. The outputs change state synchronous with
the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without extra
logic, thus simplifying multistage counter designs. Individual preset inputs
allow the circuits to be used as programmable counters. Both the Parallel
Load (PL) and the Master Reset (MR) inputs asynchronously override the
clocks.
SN54/74LS192
SN54/74LS193
PRESETTABLE BCD/ DECADE
UP/ DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/ DOWN COUNTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
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Low Power . . . 95 mW Typical Dissipation
High Speed . . . 40 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Master Reset and Parallel Load
Individual Preset Inputs
Cascading Circuitry Internally Provided
Input Clamp Diodes Limit High Speed Termination Effects
16
1
N SUFFIX
PLASTIC
CASE 648-08
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
P0
15
MR
14
TCD
13
TCU
12
PL
11
P2
10
P3
9
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
1
P1
2
Q1
3
Q0
4
CPD
5
CPU
6
Q2
7
Q3
8
GND
LOGIC SYMBOL
11
15
1
10
9
PIN NAMES
LOADING
(Note a)
HIGH
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5
4
CPU
CPD
PL
P0 P1 P2
P3
TCU
TCD
CPU
CPD
MR
PL
Pn
Qn
TCD
TCU
Count Up Clock Pulse Input
Count Down Clock Pulse Input
Asynchronous Master Reset (Clear) Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Flip-Flop Outputs (Note b)
Terminal Count Down (Borrow) Output (Note b)
Terminal Count Up (Carry) Output (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
12
MR Q0 Q1 Q2 Q3
14
3
2
6
7
13
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
碌A(chǔ)
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-351

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