SN54/74LS166
8-BIT SHIFT REGISTERS
The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 54/ 74LS standard load.
By utilizing input clamping diodes, switching transients are minimized and
system design simplified.
The LS166 is a parallel-in or serial-in, serial-out shift register and has a
complexity of 77 equivalent gates with gated clock inputs and an overriding
clear input. The shift/load input establishes the parallel-in or serial-in mode.
When high, this input enables the serial data input and couples the eight
flip-flops for serial shifting with each clock pulse. Synchronous loading occurs
on the next clock pulse when this is low and the parallel data inputs are
enabled. Serial data flow is inhibited during parallel loading. Clocking is done
on the low-to-high level edge of the clock pulse via a two input positive NOR
gate, which permits one input to be used as a clock enable or clock inhibit
function. Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow the
system clock to be free running and the register stopped on command with
the other clock input. A change from low-to-high on the clock inhibit input
should only be done when the clock input is high. A buffered direct clear input
overrides all other inputs, including the clock, and sets all flip-flops to zero.
8-BIT SHIFT REGISTERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
鈥?/div>
Synchronous Load
鈥?/div>
Direct Overriding Clear
鈥?/div>
Parallel to Serial Conversion
PARALLEL
PARALLEL INPUTS
F
11
F
E
10
E
CLEAR
9
16
1
N SUFFIX
PLASTIC
CASE 648-08
SHIFT/ INPUT OUTPUT
H
QH
G
VCC LOAD
16
15
14
13
12
SHIFT/
LOAD
H
QH
G
16
1
D SUFFIX
SOIC
CASE 751B-03
SERIAL INPUT
A
1
SERIAL
INPUT
2
A
B
3
B
C
4
C
D
5
D
CLEAR
CLOCK
INHIBIT CK
8
6
7
CLOCK CLOCK GND
INHIBIT
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
PARALLEL INPUTS
FUNCTION TABLE
INPUTS
CLEAR
L
H
H
H
H
H
SHIFT/
LOAD
X
X
L
H
H
X
CLOCK
INHIBIT
X
L
L
L
L
H
PARALLEL
CLOCK
X
L
鈫?/div>
鈫?/div>
鈫?/div>
鈫?/div>
SERIAL
A...H
X
X
X
H
L
X
X
X
a...h
X
X
X
QA
L
QA0
a
H
L
QA0
QB
L
QB0
b
QAn
QAn
QB0
L
QH0
h
QGn
QGn
QH0
INTERNAL
OUTPUTS
OUTPUT
QH
FAST AND LS TTL DATA
5-1
74LS166相關型號PDF文件下載
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英文版
OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUT(NONINVERTED)
MITSUBISHI [Mit...
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英文版
Quad 2-Input NAND Gate
FAIRCHILD
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英文版
QUAD 2-INPUT NAND GATE
ETC
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英文版
QUAD 2-INPUT NAND GATE
ETC [ETC]
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英文版
Quad 2-Input NAND Gate
FAIRCHILD ...
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英文版
QUAD 2-INPUT NAND GATE
-
英文版
QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OU...
TI
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英文版
Quadruple 2-input Positive NAND Gates(with Open Collector Ou...
HITACHI
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英文版
Quadruple 2-input Positive NAND Gates(with Open Collector Ou...
HITACHI [H...
-
英文版
QUAD 2-INPUT NAND GATE
MOTOROLA [...
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英文版
QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OU...
TI [Texas ...
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英文版
Quadruple 2-input Positive NOR Gates
HITACHI
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英文版
Quad 2-Input NOR Gate
FAIRCHILD
-
英文版
Quad 2-Input NOR Gate
FAIRCHILD ...
-
英文版
Quadruple 2-input Positive NOR Gates
HITACHI [H...
-
英文版
QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OU...
TI
-
英文版
Quadruple 2-input Positive NAND Gates(with Open Colletor Out...
HITACHI
-
英文版
Quad 2-Input NAND Gates with Open-Collector Outputs
FAIRCHILD
-
英文版
Quadruple 2-input Positive NAND Gates(with Open Colletor Out...
HITACHI [H...
-
英文版
Quad 2-Input NAND Gates with Open-Collector Outputs
FAIRCHILD ...
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