鈥?/div>
Overriding Clear Terminates Output Pulse
Compensated for VCC and Temperature Variations
DC Triggered from Active-High or Active-Low Gated Logic Inputs
Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle
Internal Timing Resistors on LS122
16
1
J SUFFIX
CERAMIC
CASE 620-09
SN54 / 74LS123
(TOP VIEW)
(SEE NOTES 1 THRU 4)
1 R
ext/
V
CC
16
C
ext
15
1
C
ext
14
1Q
13
2Q
12
2
CLR
2B
10
2A
9
16
1
N SUFFIX
PLASTIC
CASE 648-08
11
Q
CLR
Q
CLR
Q
Q
16
1
6
2
7
2
R
ext/
C
ext
8
GND
D SUFFIX
SOIC
CASE 751B-03
1
1A
2
1B
3
1
CLR
4
1Q
5
2Q
C
ext
J SUFFIX
CERAMIC
CASE 632-08
14
1
SN54 / 74LS122
(TOP VIEW)
(SEE NOTES 1 THRU 4)
R
ext/
V
CC
14
C
ext
13
NC
12
C
ext
11
NC
10
R
int
9
Q
8
R
int
Q
14
1
N SUFFIX
PLASTIC
CASE 646-06
CLR
Q
1
A1
2
A2
3
B1
4
B2
5
CLR
6
Q
7
GND
14
1
D SUFFIX
SOIC
CASE 751A-02
NC
NO INTERNAL CONNECTION.
NOTES:
1. An external timing capacitor may be connected between Cext and Rext/Cext (positive).
2. To use the internal timing resistor of the LS122, connect Rint to VCC.
3. For improved pulse width accuracy connect an external resistor between Rext/Cext and
VCC with Rint open-circuited.
4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext
and VCC.
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
FAST AND LS TTL DATA
5-197