applications. The device is byte controlled. The flip-flops
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
signal environment. The 26
鈩?/div>
series resistor helps reduce
output overshoot and undershoot.
The LCXH162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
The LCXH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
Features
I
5V tolerant control inputs and outputs
I
2.3V鈥?.6V V
CC
specifications provided
I
Equivalent 26
鈩?/div>
series resistors on outputs
I
Bushold on inputs eliminates the need for external
pull-up/pull-down resistors
I
6.2 ns t
PD
max (V
CC
=
3.3V), 20
碌
A I
CC
max
I
Power down high impedance inputs and outputs
I
鹵
12 mA output drive (V
CC
=
3.0V)
I
Implements patented noise/EMI reduction circuitry
I
Latch-up performance exceeds 500 mA
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
I
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
74LCXH162373GX
(Note 1)
74LCXH162373MEA
(Note 2)
74LCXH162373MTD
(Note 2)
Package
Number
BGA54A
(Preliminary)
MS48A
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
BGA package available in Tape and Reel only.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
漏 2001 Fairchild Semiconductor Corporation
DS500445
www.fairchildsemi.com
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