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74LCX374T Datasheet

  • 74LCX374T

  • OCTAL D-TYPE FLIP FLOP NON INVERTING 3-STATE WITH 5V TOLERAN...

  • 10頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74LCX374
OCTAL D-TYPE FLIP FLOP NON INVERTING (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
f
MAX
= 150 MHz (MIN.) at V
CC
= 3V
POWER-DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
PCI BUS LEVELS GUARANTEED AT 24mA
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
LATCH-UP PERFORMANCE EXCEEDS 500mA
ESD PERFORMANCE:
HBM >2000V; MM > 200V
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LCX374M
74LCX374T
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be
in a normal state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
It has same speed performance at 3.3V than 5V,
AC/ACT family, combined with a lower power
consumption. It has better speed performance at
3.3V than 5V LSTTL family combined with the
true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LCX374 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/10

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