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74LCX240WM Datasheet

  • 74LCX240WM

  • Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs...

  • 10頁

  • FAIRCHILD

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74LCX240 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
February 1994
Revised March 2005
74LCX240
Low Voltage Octal Buffer/Line Driver with
5V Tolerant Inputs and Outputs
General Description
The LCX240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver. The
device is designed for low voltage (2.5V or 3.3V) V
CC
appli-
cations with capability of interfacing to a 5V signal environ-
ment.
The LCX240 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V鈥?.6V V
CC
specifications provided
s
6.5 ns t
PD
max (V
CC
3.3V), 10
P
A I
CC
max
s
Power-down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
r
24 mA output drive (V
CC
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCX240WM
74LCX240SJ
74LCX240MSA
74LCX240MTC
74LCX240MTCX_NL
(Note 2)
Package
Number
M20B
M20D
MSA20
MTC20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 2:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Diagram
Connection Diagram
漏 2005 Fairchild Semiconductor Corporation
DS011993
www.fairchildsemi.com

74LCX240WM 產(chǎn)品屬性

  • 36

  • 集成電路 (IC)

  • 邏輯 - 柵極和逆變器

  • 74LCX

  • 逆變器，緩沖器

  • 2

  • 4

  • 三態(tài)

  • 2 V ~ 3.6 V

  • 10µA

  • 24mA，24mA

  • 0.7 V ~ 0.8 V

  • 1.7 V ~ 2 V

  • 6.5ns @ 3.3V，50pF

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-SOIC

  • 20-SOIC（0.295"，7.50mm 寬）

  • 管件

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