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74HCT4040 Datasheet

  • 74HCT4040

  • 12-stage binary ripple counter

  • 24頁(yè)

  • PHILIPS

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74HC4040; 74HCT4040
12-stage binary ripple counter
Rev. 03 鈥?14 September 2005
Product data sheet
1. General description
The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin
compatible with the HEF4040B series. They are speci鏗乪d in compliance with JEDEC
standard no. 7A.
The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to
Q11). The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle 鏗俰p-鏗俹p.
2. Features
s
Multiple package options
s
Complies with JEDEC standard no. 7A
s
ESD protection:
x
HBM JESD22-A114-C exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
s
Speci鏗乪d from
鈭?0 擄C
to +85
擄C
and from
鈭?0 擄C
to +125
擄C
3. Applications
s
Frequency dividing circuits
s
Time delay circuits
s
Control counters
4. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
擄
C; t
r
= t
f
= 6 ns.
Symbol
t
PHL
, t
PLH
Parameter
propagation delay
CP to Q0
Qn to Qn+1
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
-
-
14
8
-
-
ns
ns
Conditions
Min
Typ
Max
Unit
Type 74HC4040

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