M54/74HC620
M54/74HC623
OCTAL BUS TRANSCEIVER
HC620 3 STATE INVERTING HC623 3 STATE NON INVERTING
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HIGH SPEED
t
PD
= 10 ns (TYP.) AT V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 4
碌A(chǔ)
(MAX.) AT T
A
= 25
擄C
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 6 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
PIN AND FUNCTION COMPATIBLE
WITH LS620/623
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R
M74HCXXXM1R
M74HCXXXB1R
M74HCXXXC1R
DESCRIPTION
The M54/74HC620/623 are high speed CMOS
OCTAL BUS TRANSCEIVERS fabricated in silicon
2
gate C MOS technology. They have the same high
speed performance of LSTTL combined with true
CMOS low power consumption.
These octal bus transceivers are designed for asyn-
chronous two-way communication between data
buses. The control function implementation allows
maximum flexibility in timing.
These devices allow data transmission from the A
bus to B bus or from the B to the A bus depending
upon the logic levels at the enable inputs (GBA and
GAB). The enable inputs can be used to disable the
device so that the buses are effectively isolated.
The dual-enable configuration gives these devices
the capability to store data by simultaneous enabling
of GBA and GAB.
Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets
of bus lines are at high impedance, both sets of bus
lines (16 in all) will remain at their last states. The 8-
bit codes appearing on the two sets of buses will be
identical for the 鈥橦C623 or complementary for the
鈥橦C620. All inputs are equipped with protection cir-
cuits against static discharge and transient excess
voltage.
October 1992
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
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