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74HC4094 Datasheet

  • 74HC4094

  • 8 BIT SIPO SHIFT LATCH REGISTER 3-STATE

  • 12頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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M54HC4094
M74HC4094
8 BIT SIPO SHIFT LATCH REGISTER (3-STATE)
.
.
.
.
.
.
.
.
HIGH SPEED
f
MAX
= 73 MHz (TYP.) AT V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 4
碌A(chǔ)
(MAX.) AT T
A
= 25
擄C
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 4094B
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC4094F1R
M74HC4094M1R
M74HC4094B1R
M74HC4094C1R
PIN CONNECTIONS
(top view)
DESCRIPTION
The M54/74HC4094 is a high speed CMOS 8 BIT
SIPO SHIFT LATCH REGISTER fabricated with sili-
con gate C
2
MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
This device consists of an 8-bit shift register and an
8-bit latch with 3-state output buffer. Data is shifted
serially through the shift register on the positive
going transition of the clock input signal. The output
of the last stage (Qs) can be used to cascade sev-
eral devices.
Data on the Qs output is transferred to a second out-
put (Qs鈥? on the following negative transition of the
clock input signal. The data of each stage of the shift
register is provided with a latch, which latches data
on the negative going transition of the STROBE
input signal. When the STROBE input is held high,
data propagates through the latch to a 3-state output
buffer.
This buffer is enabled when OUTPUT ENABLE
input is taken high. All inputs are equipped with pro-
tection circuits against static discharge and transient
excess voltage.
February 1993
NC =
No Internal
Connection
1/12

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