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74HC4024PW Datasheet

  • 74HC4024PW

  • 7-stage binary ripple counter

  • 18頁

  • PHILIPS

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74HC4024
7-stage binary ripple counter
Rev. 03 鈥?12 November 2004
Product data sheet
1. General description
The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024
of the 4000B series. The 74HC4024 is speci鏗乪d in compliance with JEDEC
standard no. 7A.
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to
Q6).
The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle 鏗俰p-鏗俹p.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
s
Low-power dissipation
s
Complies with JEDEC standard no. 7A
s
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Speci鏗乪d from
鈭?0 擄C
to +80
擄C
and from
鈭?0 擄C
to +125
擄C.
3. Applications
s
Frequency dividing circuits
s
Time delay circuits.

74HC4024PW 產(chǎn)品屬性

  • NXP

  • 計數(shù)器 IC

  • Binary Counters

  • SOT-402

  • Tube

  • SMD/SMT

  • 96

  • 74HC4024PW,112

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