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74GTLPH1645DGGRE4 Datasheet

  • 74GTLPH1645DGGRE4

  • 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

  • 254.71KB

  • 17頁

  • TI

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SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
www.ti.com
SCES290D 鈥?OCTOBER 1999 鈥?REVISED JUNE 2005
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Member of the Texas Instruments Widebus鈩?/div>
Family
TI-OPC鈩?Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC鈩?Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Outputs (100 mA)
LVTTL Outputs (鈥?4 mA/24 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
Data-Transfer Rate and Signal Integrity in
Distributed Loads
I
off
, Power-Up 3-State, and BIAS V
CC
Support
Live Insertion
Bus Hold on A-Port Data Inputs
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DGG OR DGV PACKAGE
(TOP VIEW)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1DIR
1A1
1A2
GND
1A3
1A4
V
CC
GND
1A5
1A6
GND
1A7
1A8
GND
ERC
2A1
2A2
GND
2A3
2A4
GND
V
CC
2A5
2A6
GND
2A7
2A8
2DIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
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24
25
26
27
28
56
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54
53
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48
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46
45
44
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40
39
38
37
36
35
34
33
32
31
30
29
1OE
1B1
1B2
GND
1B3
1B4
V
CC
GND
1B5
1B6
GND
1B7
1B8
BIAS V
CC
V
REF
2B1
2B2
GND
2B3
2B4
GND
V
CC
2B5
2B6
GND
2B7
2B8
2OE
DESCRIPTION/ORDERING INFORMATION
The SN74GTLPH1645 is a high-drive, 16-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL
signal-level translation. It is partitioned as two 8-bit transceivers. The device provides a high-speed interface
between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed
(about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced
output swing (<1 V), reduced input threshold levels, improved differential input, OEC鈩?circuitry, and TI-OPC鈩?/div>
circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and
tested using several backplane models. The high drive allows incident-wave switching in heavily loaded
backplanes with equivalent load impedance down to 11
鈩?
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH1645 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V and
V
REF
= 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
REF
is the B-port differential input
reference voltage.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, TI-OPC, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 1999鈥?005, Texas Instruments Incorporated

74GTLPH1645DGGRE4 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 邏輯 - 變換器

  • 74GTLPH

  • 變換器，雙向

  • 16

  • LVTTL

  • GTLP

  • -

  • 2

  • 8

  • 無/無

  • 5.8ns

  • 3.15 V ~ 3.45 V

  • -40°C ~ 85°C

  • 56-TFSOP（0.240"，6.10mm 寬）

  • 56-TSSOP

  • 帶卷 (TR)

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