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74GTLP2033DGVRE4 Datasheet

  • 74GTLP2033DGVRE4

  • 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEI...

  • 20頁

  • TI

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SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C 鈥?JUNE 2001 鈥?REVISED SEPTEMBER 2001
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Member of the Texas Instruments
Widebus錚?Family
TI-OPC錚?Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC錚?Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Open-Drain Outputs
(100 mA)
LVTTL Outputs (鈥?4 mA/24 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?1000-V Charged-Device Model (C101)
DGG OR DGV PACKAGE
(TOP VIEW)
IMODE1
AI1
AO1
GND
AI2
AO2
V
CC
AI3
AO3
GND
AI4
AO4
AO5
AI5
GND
AO6
AI6
V
CC
AO7
AI7
GND
AO8
AI8
OMODE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
IMODE0
BIAS V
CC
B1
GND
OEAB
B2
ERC
OEAB
B3
GND
CLKAB/LEAB
B4
B5
CLKBA/LEBA
GND
B6
OEBA
V
CC
B7
LOOPBACK
GND
B8
V
REF
OMODE1
description
The SN74GTLP2033 is a high-drive, 8-bit, three-wire registered transceiver that provides inverted
LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and
flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback
path for control and diagnostics monitoring, the same functionality as the SN74FB2033. The device provides
a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result
of GTLP鈥檚 reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC錚?/div>
circuitry, and TI-OPC錚?circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have
been designed and tested using several backplane models. The high drive allows incident-wave switching in
heavily loaded backplanes with equivalent load impedance down to 11
鈩?
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2001, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

74GTLP2033DGVRE4 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 邏輯 - 專用邏輯

  • 74GTLP

  • LVTTL-TO-GTLP 可調(diào)信號沿速率寄存收發(fā)器

  • 3.15 V ~ 3.45 V

  • 8

  • -40°C ~ 85°C

  • 表面貼裝

  • 48-TFSOP（0.173"，4.40mm 寬）

  • 48-TVSOP

  • 帶卷 (TR)

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