74GTL1655
16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS
TRANSCEIVERS WITH LIVE INSERTION
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HIGH SPEED GTL/GTL+ UNIVERSAL
TRANSCEIVER :
t
PD
= 4.6 ns (MAX.) A to B at V
CC
= 3V
COMBINES D-TYPE LATCHES AND D-TYPE
FLIP-FLOPS FOR OPERATION IN
TRANSPARENT, LATCHED, OR CLOCKED
MODE
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 3.0V to 3.6V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
=24mA (MIN) at V
CC
= 3V (A PORT)
OUTPUT IMPEDANCE:
I
OL
= 100mA (MIN) at V
CC
= 3V (B PORT)
HIGH-IMPEDANCE STATE DURING POWER
UP AND POWER DOWN up to Vcc=1.5V
PERMITT LIVE INSERTION
B-PORT PRECHARGED BY BIASVcc
REDUCE NOISE ON THE LINE DURING
LIVE INSERTION
EDGE RATE-CONTROL INPUT
CONFIGURES THE B-PORT OUTPUT RISE
AND FALL TIMES
BUS HOLD ON DATA INPUTS ELIMINATES
THE NEED FOR EXTERNAL PULL-UP/
PULL-DOWN RESISTORS (A PORT)
DISTRIBUTED VCC AND GND PIN
CONFIGURATION MINIMIZES HIGH-SPEED
SWITCHING NOISE IN PARALLEL
COMUNICATIONS .
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 1655
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
T &R
74GTL1655TTR
PIN CONNECTION
DESCRIPTION
The 74GTL1655 devices are 16-bit high-drive
(100mA), low-output-impedance universal bus
transceivers designed for backplane applications.
The 74GTL1655 devices provide live-insertion
capability for backplane applications by tolerating
active signals on the data ports when the devices
are powered off. In addition, a biasing pin
preconditions the GTL/GTL+ port to minimize
disruption to an active backplane.
The edge rate-control (V
ERC
) input is provided so
the rise and fall time of the B outputs can be
configured to optimize for various backplane
loading conditions. Data flow in each direction is
controlled by output-enable (OEAB and OEBA),
December 2001
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