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74FR1074PC Datasheet

  • 74FR1074PC

  • Dual D-Type Flip-Flop

  • 69.92KB

  • 8頁

  • FAIRCHILD

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74FR74 鈥?74FR1074 Dual D-Type Flip-Flop
March 1992
Revised August 1999
74FR74 鈥?74FR1074
Dual D-Type Flip-Flop
General Description
The 74FR74 and 74FR1074 are dual D-type flip-flops with
true and complement (Q/Q) outputs. On the 74FR74, data
at the D inputs is transferred to the outputs on the rising
edge of the clock input (CP
n
). The 74FR1074 is the nega-
tive edge triggered version of this device. Both parts fea-
ture asynchronous clear (C
Dn
) and set (S
Dn
) inputs which
are low level enabled.
Features
s
74FR74 is pin-for-pin compatible with the 74F74
s
True 150 MHz f
MAX
capability on 74FR74
s
Outputs sink 24 mA and source 24 mA
s
Guaranteed pin-to-pin skew specifications
Ordering Code:
Order Number
74FR74SC
74FR74PC
74FR1074SC
74FR1074PC
Package Number
M14A
N14A
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagrams
74FR74
74FR1074
漏 1999 Fairchild Semiconductor Corporation
DS010977
www.fairchildsemi.com

74FR1074PC 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 2

  • 74F

  • D-Type Flip-Flop

  • Inverting/Non-Inverting

  • Single-Ended

  • 6.5 ns

  • - 24 mA

  • 5.5 V

  • + 70 C

  • Through Hole

  • PDIP-14

  • Rail

  • 0 C

  • 1

  • 1

  • 4.5 V

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