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74F533SCX Datasheet

  • 74F533SCX

  • 8-Bit D-Type Latch

  • 7頁

  • ETC

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74F533 Octal Transparent Latch with 3-STATE Outputs
April 1988
Revised October 2000
74F533
Octal Transparent Latch with 3-STATE Outputs
General Description
The 74F533 consists of eight latches with 3-STATE outputs
for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state. The 74F533 is the same as the
74F373, except that the outputs are inverted.
Features
s
Eight latches in a single package
s
3-STATE outputs for bus interfacing
s
Inverted version of the 74F373
Ordering Code:
Order Number
74F533SC
74F533SJ
74F533PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
漏 2000 Fairchild Semiconductor Corporation
DS009548
www.fairchildsemi.com

74F533SCX 產(chǎn)品屬性

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 鎖銷

  • 74F

  • D 型透明鎖存器

  • 8:8

  • 三態(tài)

  • 4.5 V ~ 5.5 V

  • 1

  • 6.7ns

  • 3mA，24mA

  • 0°C ~ 70°C

  • 表面貼裝

  • 20-SOIC（0.295"，7.50mm 寬）

  • 20-SOIC

  • 帶卷 (TR)

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