74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert Gate
April 1988
Revised September 2000
74F51
Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert Gate
General Description
This device contains two independent logic units, one per-
forming a 2-2 AND-OR-INVERT and the other performing a
3-3 AND-OR-INVERT function.
Ordering Code:
Order Number
74F51SC
74F51SJ
74F51PC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Unit Loading/Fan Out
Pin Names
A
n
, B
n
, C
n
, D
n
, E
n
, F
n
O
n
Description
Inputs
Outputs
U.L.
Input I
IH
/I
IL
20
碌
A/
鈭?/div>
0.6 mA
HIGH/LOW Output I
OH
/I
OL
1.0/1.0
50/33.3
鈭?/div>
1 mA/20 mA
Function Table for 3-Input Gates
Inputs
A
0
H
X
B
0
H
X
C
0
H
X
D
0
X
H
E
0
X
H
F
0
X
H
Output
O
0
L
L
H
L
=
LOW Voltage Level
Function Table for 2-Input Gates
Inputs
A
1
H
X
X
=
Immaterial
Output
C
1
X
H
D
1
X
H
O
1
L
L
H
B
1
H
X
All other combinations
H
=
HIGH Voltage Level
All other combinations
漏 2000 Fairchild Semiconductor Corporation
DS009468
www.fairchildsemi.com
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