54F 74F378 Parallel D Register with Enable
January 1995
54F 74F378
Parallel D Register with Enable
General Description
The 鈥橣378 is a 6-bit register with a buffered common En-
able This device is similar to the 鈥橣174 but with common
Enable rather than common Master Reset
Features
Y
Y
Y
Y
Y
6-bit high-speed parallel register
Positive edge-triggered D-type inputs
Fully buffered common clock and enable inputs
Input clamp diodes limit high-speed termination effects
Full TTL and CMOS compatible
Commercial
74F378PC
Military
Package
Number
N16E
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F378DM (QB)
74F378SC (Note 1)
74F378SJ (Note 1)
54F378FM (QB)
54F378LM (QB)
J16A
M16A
M16D
W16A
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and SJX
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9526鈥?
IEEE IEC
TL F 9526 鈥?2
TL F 9526 鈥?3
TL F 9526鈥?
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9526
RRD-B30M75 Printed in U S A