54F 74F377 Octal D Flip-Flop with Clock Enable
May 1995
54F 74F377
Octal D Flip-Flop with Clock Enable
General Description
The 鈥橣377 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs The common buffered
Clock (CP) input loads all flip-flops simultaneously when the
Clock Enable (CE) is LOW
The register is fully edge-triggered The state of each D in-
put one setup time before the LOW-to-HIGH clock tran-
sition is transferred to the corresponding flip-flop鈥檚 Q out-
put The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable opera-
tion
Features
Y
Y
Y
Y
Y
Y
Y
Y
Ideal for addressable register applications
Clock enable for address and data synchronization
applications
Eight edge-triggered D flip-flops
Buffered common clock
See 鈥橣273 for master reset version
See 鈥橣373 for transparent latch version
See 鈥橣374 for TRI-STATE version
Guaranteed 4000V minimum ESD protection
Commercial
74F377PC
Military
Package
Number
N20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F377DM (QB)
74F377SC (Note 1)
74F377SJ (Note 1)
54F377FM (QB)
54F377LM (QB)
J20A
M20B
M20D
W20A
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and SJX
Logic Symbols
IEEE IEC
TL F 9525 鈥?1
TL F 9525 鈥?4
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9525
RRD-B30M75 Printed in U S A