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74F109SC Datasheet

  • 74F109SC

  • Dual JK Positive Edge-Triggered Flip-Flop

  • 10頁

  • NSC

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54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
54F/74F109
November 1994
54F/74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The 鈥橣109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to 鈥橣74
data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
n
Guaranteed 4000V minimum ESD protection.
Ordering Code:
Commercial
74F109PC
See Section 0
Military
Package
Number
N16E
54F109DM (Note 2)
J16A
M16A
M16D
54F109FM (Note 2)
54F109LM (Note 2)
W16A
E20A
16-Lead (0.300" Wide) Molded Dual-in-Line
16-Lead Ceramic Dual-in-Line
16-Lead (0.150" Wide) Molded Small Outline,
JEDEC
16-Lead (0.300" Wide) Molded Small Outline,
EIAJ
16-Lead Cerpack
16-Lead Ceramic Leadless Chip Carrier, Type C
Package Description
DSXXX
74F109SC (Note 1)
74F109SJ (Note 1)
Note 1:
Devices also available in 13" reel. Use suffix = SCX and SJX.
Note 2:
Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB.
Logic Symbols
IEEE/IEC
DS009471-3
DS009471-4
DS009471-6
FAST
and TRI-STATE
are registered trademarks of National Semiconductor Corporation.
漏 1997 National Semiconductor Corporation
DS009471
www.national.com
1
PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1
cmserv
Proof
1

74F109SC 產(chǎn)品屬性

  • 48

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74F

  • 設(shè)置(預(yù)設(shè))和復(fù)位

  • JK 型

  • 差分

  • 2

  • 1

  • 125MHz

  • 5.2ns

  • 正邊沿

  • 1mA,20mA

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 16-SOIC(0.154",3.90mm 寬)

  • 管件

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