54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
54F/74F109
November 1994
54F/74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The 鈥橣109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to 鈥橣74
data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
n
Guaranteed 4000V minimum ESD protection.
Ordering Code:
Commercial
74F109PC
See Section 0
Military
Package
Number
N16E
54F109DM (Note 2)
J16A
M16A
M16D
54F109FM (Note 2)
54F109LM (Note 2)
W16A
E20A
16-Lead (0.300" Wide) Molded Dual-in-Line
16-Lead Ceramic Dual-in-Line
16-Lead (0.150" Wide) Molded Small Outline,
JEDEC
16-Lead (0.300" Wide) Molded Small Outline,
EIAJ
16-Lead Cerpack
16-Lead Ceramic Leadless Chip Carrier, Type C
Package Description
DSXXX
74F109SC (Note 1)
74F109SJ (Note 1)
Note 1:
Devices also available in 13" reel. Use suffix = SCX and SJX.
Note 2:
Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB.
Logic Symbols
IEEE/IEC
DS009471-3
DS009471-4
DS009471-6
FAST
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and TRI-STATE
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are registered trademarks of National Semiconductor Corporation.
漏 1997 National Semiconductor Corporation
DS009471
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