CGS74B305 Octal Divide-by-2 Skew Clock Driver
July 1996
CGS74B305
Octal Divide-by-2 Skew Clock Driver
General Description
These minimum skew clock drivers are designed for high
frequency Clock Generation Support (CGS) applications
These devices are ideal for duty cycle recovery applications
with internal frequency divide-by-2 circuitry The devices
guarantee minimum skew across the outputs of a given de-
vice Skew parameters are also provided as a means to
measure duty cycle requirements as those found in high
speed clocking systems
Features
Y
Y
Y
Y
Y
Functional Description
The CGS74B305 contains eight flip-flops designed to have
low skew between outputs The eight outputs (four in-phase
with CLK and four out-of-phase) toggle on successive CLK
pulses PRE and CLR inputs are provided to set Q and Q
outputs high or low independent of CLK pin
Y
Y
Clock Generation
Support (CGS) devices ideal for
high frequency signal generation or clock distribution
applications
Fabricated on National鈥檚 Advanced Bipolar FAST
TM
LSI
process
750 ps pin-to-pin output skew
Specification for transition skew to meet duty cycle
requirements
Current sourcing 24 mA and current sinking of 48 mA
Low dynamic power consumption above 20 MHz
Guaranteed 4 kV ESD protection
Logic Diagram
Connection Diagram
Pin Assignment
SOIC (M)
TL F 11751 鈥?1
Circuit description of the 鈥?05
TL F 11751 鈥?3
Pin Description
Pin Names
CLK
Q
0
鈥換
7
PRE
CLR
Description
Clock Input
Outputs
Preset
Clear
Truth Table
Inputs
CLR
L
H
L
H
H
PRE
H
L
L
H
H
CLK
X
X
X
Outputs
Q
0
鈥?Q
3
L
H
L
Q
0
Q
0
Q
4
鈥換
7
H
L
L
Q
0
Q
0
u
L
This state will not persist when CLR PRE returns to high
FAST
TM
is a trademark of National Semiconductor Corporation
C
1996 National Semiconductor Corporation
TL F 11751
RRD-B30M86 Printed in U S A
http
www national com
1
2
3
4
5
6
