CGS64 74B2529 500 ps 2 to 10 Minimum Skew Clock Driver
September 1995
CGS64 74B2529
500 ps 2 to 10 Minimum Skew Clock Driver
General Description
This minimum skew clock driver is designed for Clock Gen-
eration and Support (CGS) applications operating from
33 MHz to 80 MHz The devices guarantee minimum output
skew across the outputs of a given device
Skew parameters are also provided as a means to measure
duty cycle requirements as those found in high speed clock-
ing systems The 鈥?529 is a minimum skew clock driver with
two selectable inputs driving ten outputs
The SEL pin is used to determine which CLKn will have an
active effect on the outputs of the circuit When SEL
e
1
the CLK1 input is selected and when SEL
e
0 the CLK0
input is selected The non-selected CLKn input will not have
any effect on the logical output level of the circuit The out-
put pins act as a single entity and will follow the state of the
CLK inputs
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Clock Generation and Support (CGS) devices
Ideal for high frequency signal generation or clock
distribution applications
CGS74B version features National鈥檚 Advanced Bipolar
FAST LSI process
2-to-10 low skew clock distribution
500 ps pin-to-pin output skew (V package)
Specification for transition skew to meet duty cycle
requirements
20-center pin V
CC
and GND configuration or PLCC to
minimize high speed switching noise
Current sourcing 48 mA and current sinking of 64 mA
Low dynamic power consumption above 20 MHz
Guaranteed 4 kV ESD protection
Logic Symbols
Connection Diagrams
Pin Assignment
SOIC
TL F 11923鈥?
Pin Descriptlon
Pin
Names
CLK0 CLK1
O0鈥揙9
SEL
Description
Clock Input
Outputs
Clock Select
TL F 11923 鈥?2
TL F 11923 鈥?3
Pin Assignment
for PLCC
Inputs
CLK0
L
H
X
X
CLK1
X
X
L
H
SEL
L
L
H
H
Outputs
O0鈥揙9
L
H
L
H
L
e
Low Logic Level
H
e
High Logic Level
X
e
Immaterial
FAST is a registered trademark of National Semiconductor Corporation
C
1996 National Semiconductor Corporation
TL F 11923 鈥?4
RRD-B30M106 Printed in U S A
TL F 11923
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