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74AVCH2T45 Datasheet

  • 74AVCH2T45

  • Dual-bit, dual-supply voltage level translator/transceiver; ...

  • 29頁

  • PHILIPS

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74AVCH2T45
Dual-bit, dual-supply voltage level translator/transceiver;
3-state
Rev. 01 鈥?3 July 2007
Product data sheet
1. General description
The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level
translation. It features two data input-output ports (nA and nB), a direction control input
(DIR) and dual supply pins (V
CC(A)
and V
CC(B)
). Both V
CC(A)
and V
CC(B)
can be supplied at
any voltage between 0.8 V and 3.6 V making the device suitable for translating between
any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR
are referenced to V
CC(A)
and pins nB are referenced to V
CC(B)
. A HIGH on DIR allows
transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.
The device is fully speci鏗乪d for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging back鏗俹w current through the
device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, both A and B are in the high-impedance OFF-state.
The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or
鏗俹ating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features
I
Wide supply voltage range:
N
V
CC(A)
: 0.8 V to 3.6 V
N
V
CC(B)
: 0.8 V to 3.6 V
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-12 (0.8 V to 1.3 V)
N
JESD8-11 (0.9 V to 1.65 V)
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 3B exceeds 8000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Maximum data rates:
N
500 Mbps (1.8 V to 3.3 V translation)
N
320 Mbps (< 1.8 V to 3.3 V translation)
N
320 Mbps (translate to 2.5 V or 1.8 V)

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