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74AVC16722DGGRE4 Datasheet

  • 74AVC16722DGGRE4

  • 22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

  • 201.64KB

  • 12頁

  • TI

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SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166H 鈥?DECEMBER 1998 鈥?REVISED JUNE 2000
D
D
D
D
Member of the Texas Instruments
Widebus
鈩?/div>
Family
EPIC
鈩?/div>
(Enhanced-Performance Implanted
CMOS) Submicron Process
DOC
鈩?/div>
(Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With I
OH
and I
OL
of
鹵24
mA at 2.5-V V
CC
D
D
D
D
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class I
Packaged in Thin Shrink Small-Outline
Package
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V
OL
vs I
OL
and V
OH
vs I
OH
curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,
AVC
Logic Family Technology and Applications,
literature number SCEA006, and
Dynamic Output Control (DOC
鈩?/div>
)
Circuitry Technology and Applications,
literature number SCEA009.
3.2
2.8
V
OL
鈥?Output Voltage 鈥?V
2.4
2.0
1.6
VCC = 2.5 V
1.2
VCC = 1.8 V
0.8
0.4
0
17
34
51
68
85 102 119
IOL 鈥?Output Current 鈥?mA
136
153
170
VCC = 3.3 V
TA = 25擄C
Process = Nominal
鈥?Output Voltage 鈥?V
TA = 25擄C
Process = Nominal
2.8
2.4
2.0
1.6
1.2
0.8
V
OH
VCC = 3.3 V
0.4
VCC = 2.5 V
VCC = 1.8 V
鈥?2
鈥?6
0
鈥?60 鈥?44 鈥?28 鈥?12 鈥?6 鈥?0 鈥?4 鈥?8
IOH 鈥?Output Current 鈥?mA
Figure 1. Output Voltage vs Output Current
This 22-bit flip-flop is operational at 1.2-V to 3.6-V V
CC
, but is designed specifically for 1.65-V to 3.6-V V
CC
operation.
The 22 flip-flops of the SN74AVC16722 are edge-triggered D-type flip-flops with clock-enable (CLKEN) input.
On the positive transition of the clock (CLK) input, the device stores data into the flip-flops if CLKEN is low. If
CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the 22 outputs in either a normal logic state (high or low) or the
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC, EPIC, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

74AVC16722DGGRE4 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74AVC

  • 標(biāo)準(zhǔn)

  • D 型總線

  • 三態(tài)非反相

  • 1

  • 22

  • 80MHz

  • 7.7ns

  • 正邊沿

  • 12mA，12mA

  • 1.4 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 64-TFSOP （0.240"，6.10mm 寬）

  • 帶卷 (TR)

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