74AUP1G14
Low-power Schmitt-trigger inverter
Rev. 01 鈥?20 July 2005
Product data sheet
1. General description
The 74AUP1G14 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully speci鏗乪d for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging back鏗俹w current through
the device when it is powered down.
The 74AUP1G14 provides a single inverting Schmitt-trigger which accepts standard input
signals. It is capable of transforming slowly changing input signals into sharply de鏗乶ed,
jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
(th)LH
and the negative voltage V
(th)HL
is de鏗乶ed as the input
hysteresis voltage V
hys
.
2. Features
s
Wide supply voltage range from 0.8 V to 3.6 V
s
High noise immunity
s
ESD protection:
x
HBM JESD22-A114-C exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
x
CDM JESD22-C101-C exceeds 1000 V
s
Low static power consumption; I
CC
= 0.9
碌A(chǔ)
(maximum)
s
Latch-up performance exceeds 100 mA per JESD 78 Class II
s
Inputs accept voltages up to 3.6 V
s
Low noise overshoot and undershoot < 10 % of V
CC
s
I
OFF
circuitry provides partial Power-down mode operation
s
Multiple package options
s
Speci鏗乪d from
鈭?0 擄C
to +85
擄C
and
鈭?0 擄C
to +125
擄C
3. Applications
s
Wave and pulse shaper
s
Astable multivibrator
s
Monostable multivibrator