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74AUP1G125DRLRG4 Datasheet

  • 74AUP1G125DRLRG4

  • LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

  • 15頁(yè)

  • TI

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SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES595E 鈥?JULY 2004 鈥?REVISED JULY 2005
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Available in the Texas Instruments
NanoStar鈩?and NanoFree鈩?Packages
Low Static-Power Consumption
(I
CC
= 0.0
碌A(chǔ)
Max)
Low Dynamic-Power Consumption
(C
pd
= 4 pF Typ at 3.3 V)
Low Input Capacitance (C
i
= 1.5 pF Typ)
Low Noise 鈥?Overshoot and Undershoot
<10% of V
CC
Input-Disable Feature Allows Floating Input
Conditions
I
off
Supports Partial-Power-Down Mode
Operation
Input Hysteresis Allows Slow Input Transition
and Better Switching Noise Immunity at Input
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Wide Operating V
CC
Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
t
pd
= 4.6 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
鈥?2000-V Humna-Body Model
(A114-B, Class II)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
ESD Protection Exceeds
鹵5000
V With
Human-Body Model
DRL PACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
OE
A
GND
1
5
V
CC
OE
A
1
2
3
5
V
CC
OE
A
GND
1
2
3
5
V
CC
Y
GND
A
OE
3 4
2
1 5
Y
V
CC
2
4
GND
4
4
Y
3
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire V
CC
range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figures 1 and 2).
xxxx
Switching Characteristics
Static-Power Consumption
(碌A(chǔ))
100%
80%
60%
40%
20%
0%
AUP
鈥?/div>
Single, dual, and triple gates
Dynamic-Power Consumption
(pF)
100%
80%
Voltage 鈭?V
3.5
3
2.5
2
1.5
1
0.5
0
鈭?.5
Input
at 25 MHz
鈥?/div>
Output
3.3-V
Logic
鈥?/div>
60%
40%
20%
0%
3.3-V
LVC
Logic
鈥?/div>
AUP
0
5
10
15
20 25 30
Time 鈭?ns
35
40
45
鈥?/div>
AUP1G08 data at C = 15 pF
L
Figure 1. AUP 鈥?The Lowest-Power Family
Figure 2. Excellent Signal Integrity
xxx
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2004鈥?005, Texas Instruments Incorporated

74AUP1G125DRLRG4 產(chǎn)品屬性

  • 4,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74AUP

  • 緩沖器/線路驅(qū)動(dòng)器，非反相

  • 1

  • 1

  • 4mA，4mA

  • 0.8 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • SOT-553

  • SOT-5

  • 帶卷 (TR)

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