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74AUC2G241DCURE4 Datasheet

  • 74AUC2G241DCURE4

  • DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS

  • 13頁

  • TI

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SN74AUC2G241
DUAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES535A 鈥?DECEMBER 2003 鈥?REVISED MARCH 2005
FEATURES
鈥?/div>
鈥?/div>
Available in the Texas Instruments
NanoStar鈩?and NanoFree鈩?Packages
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
I
off
Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max t
pd
of 1.9 ns at 1.8 V
Low Power Consumption, 10
碌A(chǔ)
at 1.8 V
鹵8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE
(TOP VIEW)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1OE
1A
2Y
GND
1
2
3
4
8
7
6
5
V
CC
2OE
1Y
2A
YEP OR YZP PACKAGE
(BOTTOM VIEW)
GND
2Y
1A
1OE
4 5
3 6
2 7
1 8
2A
1Y
2OE
V
CC
DESCRIPTION/ORDERING INFORMATION
This dual buffer/driver is operational at 0.8-V to 2.7-V V
CC
, but is designed specifically for 1.65-V to 1.95-V V
CC
operation.
The SN74AUC2G241 is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is
low or 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high or 2OE is low,
the outputs are in the high-impedance state.
NanoStar鈩?and NanoFree鈩?package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar鈩?鈥?WCSP (DSBGA)
0.23-mm Large Bump 鈥?YEP
鈥?0擄C to 85擄C
NanoFree鈩?鈥?WCSP (DSBGA)
0.23-mm Large Bump 鈥?YZP (Pb-free)
SSOP 鈥?DCT
VSSOP 鈥?DCU
(1)
(2)
Tape and reel
Tape and reel
Tape and reel
Tape and reel
ORDERABLE PART NUMBER
SN74AUC2G241YEPR
_ _ _U2_
SN74AUC2G241YZPR
SN74AUC2G241DCTR
SN74AUC2G241DCUR
U41_ _ _
U2_
TOP-SIDE MARKING
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
鈰?/div>
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2003鈥?005, Texas Instruments Incorporated

74AUC2G241DCURE4 產(chǎn)品屬性

  • 3,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器

  • 74AUC

  • 緩沖器/線路驅(qū)動器，非反相

  • 2

  • 1

  • 9mA，9mA

  • 0.8 V ~ 2.7 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 8-VFSOP（0.091"，2.30mm 寬）

  • US8

  • 帶卷 (TR)

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