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Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable
Package Options include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
Dependable Texas Instruments Quality and
Reliability
SN54ALS鈥? SN54AS鈥?. . . J PACKAGE
SN74ALS鈥? SN74AS鈥?. . . D OR N PACKAGE
(TOP VIEW)
CLR
CLK
A
B
C
D
ENP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
description
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. The 鈥橝LS160B,
鈥橝LS162B, 鈥橝S160, and 鈥橝S162 are decade
counters, and the 鈥橝LS161B, 鈥橝LS163B, 鈥橝S161,
and 鈥橝S163 are 4-bit binary counters. Synchro-
nous operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincident with each other when so
instructed by the count-enable inputs and internal
gating. This mode of operation eliminates the
output counting spikes that are normally asso-
ciated with asynchronous (ripple clock)
counters. A buffered clock input triggers the four
flip-flops on the rising (positive-going) edge of the
clock input waveform.
SN54ALS鈥? SN54AS鈥?. . . FK PACKAGE
(TOP VIEW)
A
B
NC
C
D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
CLK
CLR
NC
VCC
RCO
Q
A
Q
B
NC
Q
C
Q
D
NC鈥揘o internal connection
Copyright
漏
1986, Texas Instruments Incorporated
5BASIC
These counters are fully programmable; that is, they may be preset to any number between 0 and 9, or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs.
The clear function for the 鈥橝LS160B, 鈥橝LS161B, 鈥橝S160, and 鈥橝S161 is asynchronous and a low level at the clear
input sets all four of the flip-flop outputs low regardless of the levels of the clock, load, or enable inputs. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to the clear input to
synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry
output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the
ripple carry output. The ripple carry output (RCO) thus enabled will produce a high-level pulse while the count
is maximum (9 or 15 with Q
A
high). This high-level overflow ripple carry pulse can be used to enable successive
cascaded stages. Transitions at the ENP or ENT are allowed regardless of the level of the clock input.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting
the stable setup and hold times.
The SN54ALS160B through SN54ALS163B and SN54AS160 through SN54AS163 are characterized for
operation over the full military temperature range of 鈥?55擄C to 125擄C. The SN74ALS160B through
SN74ALS163B and SN74AS160 through SN74AS163 are characterized for operation from 0擄C to 70擄C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
ENP
GND
NC
LOAD
ENT
1
1
2
3
4
5
6
7
8
9
10
11
