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74ALVTH16374ZQLR Datasheet

  • 74ALVTH16374ZQLR

  • 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-S...

  • 16頁(yè)

  • TI

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SN54ALVTH16374, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES068F 鈥?JUNE 1996 鈥?REVISED JANUARY 1999
D
D
D
D
D
D
D
D
D
D
D
D
D
State-of-the-Art Advanced BiCMOS
Technology (ABT)
Widebus
鈩?/div>
Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
CC
)
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25擄C
High Drive (鈥?4/24 mA at 2.5-V and
鈥?2/64 mA at 3.3-V V
CC
)
Power Off Disables Outputs, Permitting
Live Insertion
High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
CC
+ 0.5 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
SN54ALVTH16374 . . . WD PACKAGE
SN74ALVTH16374 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
description
The 鈥橝LVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V
or 3.3-V V
CC
operation, but with the capability to provide a TTL interface to a 5-V system environment. These
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK), the flip-flops store the logic levels set up at the data (D) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
漏
1999, Texas Instruments Incorporated
鈥?/div>
DALLAS, TEXAS 75265
1

74ALVTH16374ZQLR 產(chǎn)品屬性

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74ALVTH

  • 標(biāo)準(zhǔn)

  • D 型總線

  • 三態(tài)非反相

  • 2

  • 8

  • 150MHz

  • 1.5ns

  • 正邊沿

  • 8mA，8mA

  • 2.3 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-VFBGA

  • 帶卷 (TR)

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