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74ALVCH32973ZKER Datasheet

  • 74ALVCH32973ZKER

  • 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIG...

  • 13頁

  • TI

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SN74ALVCH32973
16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH EIGHT INDEPENDENT BUFFERS
SCES436C 鈥?APRIL 2003 鈥?REVISED SEPTEMBER 2004
FEATURES
鈥?/div>
鈥?/div>
Member of the Texas Instruments Widebus+鈩?/div>
Family
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
鈥?/div>
鈥?/div>
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This device contains eight independent noninverting buffers and a 16-bit noninverting bus transceiver and D-type
latch designed for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH32973 is particularly suitable for demultiplexing an address/data bus into a dedicated address
bus and dedicated data bus. The device is used where there is asynchronous bidirectional communication
between the A and B data bus, and the address signals are latched and buffered on the Q bus. The
control-function implementation minimizes external timing requirements.
This device can be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one
16-bit transceiver, and one 16-bit latch. It allows data transmission from the A bus to the B bus or from the B bus
to the A bus, depending on the logic level at the direction-control (DIR) input. The transceiver output-enable
(TOE) input can be used to disable the transceivers so that the A and B buses effectively are isolated.
When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q
outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE) input can be used to place
the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the
high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE does not affect
internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power down, LOE and TOE should be tied to V
CC
through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of
the drivers.
The eight independent noninverting buffers perform the Boolean function Y = D and are independent of the state
of DIR, TOE, LE, and LOE.
The A and B I/Os and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data
inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
T
A
-40擄C to 85擄C
LFBGA - GKE
LFBGA - ZKE (Pb-free)
PACKAGE
(1)
Tape and reel
ORDERABLE PART NUMBER
SN74ALVCH32973KR
74ALVCH32973ZKER
TOP-SIDE MARKING
ACH973
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2003鈥?004, Texas Instruments Incorporated

74ALVCH32973ZKER 產(chǎn)品屬性

  • 1

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器

  • 74ALVCH

  • 收發(fā)器，非反相

  • 2

  • 8

  • 24mA，24mA

  • 1.65 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 96-LFBGA

  • 96-PBGA MICROSTAR（13.6x5.6）

  • Digi-Reel®

  • 296-18282-6

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