74ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold
September 2001
Revised February 2002
74ALVCH16374
Low Voltage 16-Bit D-Type Flip-Flop with Bushold
General Description
The ALVCH16374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The ALVCH16374 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH16374 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output compatibility up to 3.6V.
The 74ALVCH16374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V to 3.6V V
CC
supply operation
s
3.6V tolerant control inputs and outputs
s
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s
t
PD
4.2 ns max for 3.0V to 3.6V V
CC
5.3 ns max for 2.3V to 2.7V V
CC
7.8 ns max for 1.65V to 1.95V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
Ordering Code:
Order Number
74ALVCH16374T
(Note 1)
Package
Number
MTD48
Package Descriptions
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
漏 2002 Fairchild Semiconductor Corporation
DS500627
www.fairchildsemi.com