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74ALVCH16373/D Datasheet

  • 74ALVCH16373/D

  • Low-Voltage 16-Bit Transparent Latch with Bus Hold 1.8/2.5/3...

  • 143.62KB

  • 12頁

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74ALVCH16373
Low-Voltage 16-Bit
Transparent Latch with Bus
Hold 1.8/2.5/3.3 V
(3鈥揝tate, Non鈥揑nverting)
http://onsemi.com
The 74ALVCH16373 is an advanced performance, non鈥搃nverting
16鈥揵it transparent latch. It is designed for very high鈥搒peed, very
low鈥損ower operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCXH16373 is byte controlled, with each byte functioning
identically, but independently. Each byte has separate Output Enable
and Latch Enable inputs. These control pins can be tied together for
full 16鈥揵it operation.
The 74ALVCH16373 contains 16 D鈥搕ype latches with 3鈥搒tate
3.6 V鈥搕olerant outputs. When the Latch Enable (LEn) inputs are
HIGH, data on the Dn inputs enters the latches. In this condition, the
latches are transparent, (a latch output will change state each time its D
input changes). When LE is LOW, the latch stores the information that
was present on the D inputs a setup time preceding the
HIGH鈥搕o鈥揕OW transition of LE. The 3鈥搒tate outputs are controlled
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches. The data inputs include active bushold circuitry,
eliminating the need for external pull鈥搖p resistors to hold unused or
floating inputs at a valid logic state.
MARKING DIAGRAM
48
48
74ALVCH16373DT
1
AWLYYWW
TSSOP鈥?8
DT SUFFIX
CASE 1201
A
WL
YY
WW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN NAMES
Pins
OEn
LEn
D0鈥揇15
O0鈥揙15
Function
Output Enable Inputs
Latch Enable Inputs
Inputs
Outputs
鈥?/div>
Designed for Low Voltage Operation: V
CC
= 1.65 鈥?3.6 V
鈥?/div>
3.6 V Tolerant Inputs and Outputs
鈥?/div>
High Speed Operation: 3.6 ns max for 3.0 to 3.6 V
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
4.5 ns max for 2.3 to 2.7 V
6.8 ns max for 1.65 to 1.95 V
Static Drive:
鹵24
mA Drive at 3.0 V
鹵12
mA Drive at 2.3 V
鹵4
mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
鈥?/div>
Near Zero Static Supply Current in All Three Logic States (40
mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds
鹵250
mA @ 125擄C
ESD Performance: Human Body Model >2000V; Machine Model >200V
Second Source to Industry Standard 74ALVCH16373
ORDERING INFORMATION
Device
74ALVCH16373DTR
Package
TSSOP
Shipping
2500/Tape & Reel
鈥燭o ensure the outputs activate in the 3鈥搒tate condition, the output enable pins
should be connected to V
CC
through a pull鈥搖p resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
漏
Semiconductor Components Industries, LLC, 2002
1
September, 2002 鈥?Rev. 1
Publication Order Number:
74ALVCH16373/D

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