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74ALVCH16245T Datasheet

  • 74ALVCH16245T

  • BUS TRANSCEIVER|DUAL|8-BIT|AVC/ALVC-CMOS|TSSOP|48PIN|PLASTIC

  • 74.44KB

  • 9頁

  • ETC

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74ALVCH16245
LOW VOLTAGE CMOS 16-BIT TRANSCEIVER (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
s
s
s
s
s
s
s
s
s
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
PD
= 3.0 ns (MAX.) at V
CC
= 3.0 to 3.6V
t
PD
= 3.7 ns (MAX.) at V
CC
= 2.3 to 2.7V
t
PD
=6 ns (MAX.) at V
CC
= 1.65V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3.0V
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 2.3V
|I
OH
| = I
OL
= 4mA (MIN) at V
CC
= 1.65V
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V
BUS HOLD PROVIDED ON DATA INPUTS
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16245
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
T&R
74ALVCH16245T
PIN CONNECTION
DESCRIPTION
The 74ALVCH16245 is a low voltage CMOS 16
BIT BUS TRANSCEIVER fabricated with
sub-micron silicon gate and five-layer metal wiring
C
2
MOS technology. It is ideal for low power and
very high speed 1.65 to 3.6V applications; it can
be interfaced to 3.6V signal environment for both
inputs and outputs.
.This IC is intended for two-way asynchronous
communication between data busses; the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the busses are
effectively isolated.
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
March 2002
1/9

74ALVCH16245T 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器

  • 74ALVCH

  • 收發(fā)器，非反相

  • 2

  • 8

  • 24mA，24mA

  • 1.65 V ~ 3.6 V

  • -55°C ~ 125°C

  • 表面貼裝

  • 48-TFSOP（0.240"，6.10mm 寬）

  • 48-TSSOP

  • 帶卷 (TR)

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