74ALVCH16244
LOW VOLTAGE CMOS 16-BIT BUS BUFFER (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
PD
= 3.0 ns (MAX.) at V
CC
= 3.0 to 3.6V
t
PD
= 3.7 ns (MAX.) at V
CC
= 2.3 to 2.7V
t
PD
= 5.1 ns (MAX.) at V
CC
= 1.65V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3.0V
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 2.3V
|I
OH
| = I
OL
= 4mA (MIN) at V
CC
= 1.65V
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V
BUS HOLD PROVIDED ON DATA INPUTS
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16244
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
T&R
74ALVCH16244TTR
PIN CONNECTION
DESCRIPTION
The 74ALVCH16244 is a low voltage CMOS 16
BIT BUS BUFFER (NON INVERTED) fabricated
with sub-micron silicon gate and five-layer metal
wiring C
2
MOS technology. It is ideal for low power
and very high speed 1.65 to 3.6V applications; it
can be interfaced to 3.6V signal environment for
both inputs and outputs.
Any nG output control governs four BUS
BUFFERS. Output Enable input (nG) tied together
gives full 16-bit operation.
When nG is LOW, the outputs are enabled. When
nG is HIGH, the output are in high impedance
state.
Active bus-hold circuitry is provided to hold
unused or floating data inputs at a valid logic level.
This device is designed to be used with 3 state
memory address drivers, etc.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2002
1/9
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.