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74ALVCH16244/D Datasheet

  • 74ALVCH16244/D

  • Low-Voltage 16-Bit Buffer with Bus Hold 1.8/2.5/3.3 V

  • 138.24KB

  • 12頁(yè)

  • ETC

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74ALVCH16244
Low-Voltage 16-Bit Buffer
with Bus Hold 1.8/2.5/3.3 V
(3鈥揝tate, Non鈥揑nverting)
The 74ALVCH16244 is an advanced performance, non鈥搃nverting
16鈥揵it buffer. It is designed for very high鈥搒peed, very low鈥損ower
operation in 1.8 V, 2.5 V or 3.3 V systems.
The 74ALVCH16244 is nibble controlled with each nibble
functioning identically, but independently. The control pins may be
tied together to obtain full 16鈥揵it operation. The 3鈥搒tate outputs are
controlled by an Output Enable (OEn) input for each nibble. When
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are
in the high impedance state. The data inputs include active bushold
circuitry, eliminating the need for external pull鈥搖p resistors to hold
unused or floating inputs at a valid logic state.
http://onsemi.com
MARKING DIAGRAM
48
48
74ALVCH16244DT
1
AWLYYWW
鈥?/div>
Designed for Low Voltage Operation: V
CC
= 1.65 鈥?3.6 V
鈥?/div>
3.6 V Tolerant Inputs and Outputs
鈥?/div>
High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
3.7 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
Static Drive:
鹵24
mA Drive at 3.0 V
鹵12
mA Drive at 2.3 V
鹵4
mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
鈥?/div>
Near Zero Static Supply Current in All Three Logic States (40
mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds
鹵250
mA @ 125擄C
ESD Performance: Human Body Model >2000V; Machine Model >200V
Second Source to Industry Standard 74ALVCH16244
TSSOP鈥?8
DT SUFFIX
CASE 1201
A
WL
YY
WW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
74ALVCH16244DTR
Package
TSSOP
Shipping
2500/Tape & Reel
鈥燭o ensure the outputs activate in the 3鈥搒tate condition, the output enable pins
should be connected to V
CC
through a pull鈥搖p resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
漏
Semiconductor Components Industries, LLC, 2002
1
September, 2002 鈥?Rev. 1
Publication Order Number:
74ALVCH16244/D

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